1. Field of the Invention
The present invention relates to a division unit, an image analysis unit and a display apparatus using the same. More particularly, the present invention relates to a division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale.
2. Description of Related Art
Display apparatus including the liquid crystal monitor, the liquid crystal television and the plasma television have played an important role in our modern-day life.
Due to intrinsic defects in a display panel (for example, a liquid crystal display panel), an image analysis at the system end is often required to compensate these defects. In an image analysis, a large number of mathematical computations are performed to obtain an overall average gray scale value of the image. The overall average gray scale value thus obtained can be used, for example, to adjust the contrast or the dynamic backlight. Using a scanning frequency of 60 Hz as an example, a total of 60 frames are scanned every second. However, to improve the image quality, it is preferable to obtain an overall average gray scale value of the image between two consecutive scanning operations for adjusting the contrast or the dynamic backlight.
The overall average gray scale value of an image is defined as follows:(AVG—R+AVG—G+AVG—B)/3=AVG—L  (1)where AVG_R represents the average gray scale value of all red pixels, AVG_G represents the average gray scale value of all green pixels, AVG_B represents the average gray scale value of all blue pixels, and AVG_L is the overall average gray scale value. In turn, AVG_R, AVG_G and AVG_B are defined as follows:AVG—R=TOTAL—R/RES  (2)AVG—G=TOTAL—G/RES  (3)AVG—B=TOTAL—B/RES  (4)where RES represents the resolution of the display panel (using a resolution of 800*480 as an example in the following description), TOTAL_R represents the sum of all the gray scale signals of the red pixels, TOTAL_G represents the sum of all the gray scale signals of the green pixels, and TOTAL_B represents the total of all the gray scale signals of the blue pixels. Putting formulas (2) to (4) into formula (1), the following equation is obtained:
                                                        AVG_L              =                            ⁢                                                (                                      TOTAL_R                    +                    TOTAL_G                    +                    TOTAL_B                                    )                                /                                                                                                      ⁢                              (                                  800                  *                  480                  *                  3                                )                                                                                                        =                                ⁢                                  TOTAL_L                  /                  1152000                                            ,                                                          (        5        )            where TOTAL_L represents the total of all the gray scale signals of the image.
When an image is input, accumulating all the gray scale signals of this image will produce the total of the gray scale signals, hereinafter referred as a totaled gray scale signal TOTAL_L. In other words, a simple cumulative circuit can be used to obtain the totaled gray scale signals. In general, the totaled gray scale signal TOTAL_L is a variable that changes according to the input image. In formula (5), the denominator is a fixed value because the resolution of the finished display panel is fixed. At present, there are a few conventional techniques for implementing the division to obtain the overall average gray scale value of the image, which are respectively explained in the following.
The first conventional technique is to use a dedicated application specific integrated circuit (ASIC) to perform the division. However, an extra IC chip is needed so that additional cost and additional circuit area are required.
The second conventional technique is to custom design a division computational circuit such as a special divider or a look-up table scheme. In the following, a divider and a look-up table scheme are introduced respectively.
A typical divider is designed as a shift divider whose algorithmic flow is shown in FIG. 1. First, in step S11, parameters A, M, M, Q and Count are initialized. Here, the parameter A represents the remainder whose initial value is 0. M is the divisor and it has a value 3 (whose binary value is 0011), for example. Q is the dividend, but ultimately, it also represents the quotient (that is, the answer). The value of Q is 7 (whose binary value is 0111), for example. Count represents a bit parameter.
In step S12, the parameters A and Q are shifted to the left by one bit. In step S13, set A=A−M. In step S14, the value of A is checked to determine if it is smaller than 0. If the value of A is not smaller than 0, then set Q0=1, where Q0 represents the lowest bit of the parameter Q as shown in step S15. However, if A is smaller than 0, then set Q0=0 and A=A+M as shown in step S16.
Then, set Count=Count−1 as shown in step S17. Then, the renewed parameter Count is checked to determine if it is 0 as shown in step S18. If the parameter Count is not 0, then the flow returns to step S12. However, if the parameter Count is 0, it means the remainder A and the quotient Q have already been found as shown in step S19.
In the design of a common micro-controller, a 4-bit division computation requires 13 steps. In other words, the computation requires 13 clock cycles to complete. Therefore, if the digital circuit is designed according to shift division and integrating some of the steps within a single clock cycle, the 4-bit division still requires at least 4 clock cycles.
Using a resolution of 800*480 as an example, the maximum possible value of the total gray scale values (using an 8-bit gray scale signal as an example) of the image is 800*480*3*255=293,760,000 so that the number of bits is log2293,760,000=28.13≈29. Therefore, if a shift division method is used to compute the average gray scale value, a total of at least 29 clock cycles is required to finish the job, which is quite time-consuming.
In the table look-up method, the dividend is separated into a plurality of groups each having an identical number of bits. Then, through a look-up method, a plurality of quotient groups is found. Thereafter, the bits are regrouped together to give the correct answer. FIG. 2 is a division circuit that uses a look-up table. As shown in FIG. 2, the look-up tables (LUT) 21 to 23 are used for finding a number of corresponding quotient groups and the shift units 24 to 26 are used for shifting the results obtained from the LUT 21 to 23. Finally, the adder 27 sums up the results of the shift units 24 to 26 to form a quotient. In the example shown in FIG. 2, the dividend has 29 bits and the quotient has 8 bits.
Although the divider occupies a smaller circuit area, it requires more clock cycles to obtain the same computational result so that the efficiency of the image analysis is cut back. On the other hand, although the look-up table method is fast to obtain the computational result, it demands more memory and hence has to occupy more circuit area.
Therefore, it is preferable to have a division unit, an image analysis unit and a display apparatus using the same that use a simpler computational method to speed up the finding of overall average gray scale value without occupying too much circuit area.